1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly, to power and ground metallization routing in a multi-metal layer semiconductor device having a plurality of basic cell circuits such as standard cells and gate array cells.
2. Description of the Related Art
FIG. 1 illustrates a conventional integrated circuit having a number of rows 3 of cells 5. The cells can have various widths W1, W2, W3, etc. and can be separated by small gaps (not shown). Power and ground are supplied to each cell from power and ground busses 7 and 9 via primary power and ground distributions 60 and 50, respectively. The primary power and ground distributions are typically laid out in the first metallization layer (i.e., "metal 1"). Moreover, metals in adjacent layers are laid out perpendicular to each other. That is, for example in a four-metal layer integrated circuit, wirings in the first and third metallization layers are laid out in one direction, and wirings on the substrate surface (e.g. polygate) and the second and fourth metallization layers are laid out in a direction perpendicular to the wirings in the first and third metallization layers.
As integration increases, rows 3 begin to abut with each other, causing the distance D1 to shrink to such a degree that the availability of the space between rows as channels for routing interconnections between cells in metal 1 is eliminated. Over-the-cell routers and other tools are thus required to route such interconnections in higher metal layers.
FIG. 2 illustrates the layout of a basic cell 5 that can be included in such a conventional integrated circuit as is illustrated in FIG. 1. It includes a PFET device region 10, a NFET device region 20, polygate 30, P-N device intraconnection 40, primary ground distribution 50, and primary power distribution 60. Contacts 70 connect power from primary power distribution 60 to the PFET device region, and contacts 80 connect ground from primary ground distribution 50 to the NFET device region. Input pins 85 are provided to connect devices in this cell with devices in other cells by contact to polygate 30 through contact 95.
As can be seen, the primary power and ground distributions are laid out in metal 1 in an east-west direction. P-N intraconnection 40 and input pins 85 are also typically laid out in the first metallization layer. As should be apparent, to connect devices in cells in other rows to the input pins 85 and output pins (typically via connection to P-N intraconnection 40) of cell 5, such connections must be routed up and over the primary power and ground distributions through higher metal layers and then back down to metal 1 through vias and contact holes and the like.
FIG. 3 is a side plan view of the basic cell in FIG. 2 taken along sectional line 3--3. It shows primary power distribution 60 formed as the first metal layer over PFET device region 10, with polygate 30 (i.e., a gate formed of a layer of doped polysilicon on the substrate) and first insulator layer 90 interposed therebetween. Device region 10 is formed in substrate 1 and is separated from other device regions by oxide 35. Gate oxide layer 25 is interposed between polygate 30 and device region 10. Input pin 85 is connected to polygate 30 by contact 95 through first insulator layer 90.
The conventional technique of routing primary power and ground distributions in metal 1 is fraught with many problems. First, for example, due to the requirement of providing P-N intraconnections such as 40, and the fact that cell integration restricts the availability of cell interconnections between rows, very few cell interconnections can be routed in metal 1. Meanwhile, it is generally desirable to route as many interconnections as possible in lower metal layers so as to conserve routing resources in upper metal layers, and thus facilitate reduced average wire lengths.
Second, as cell integration increases, the number of devices per square area of the die increases, and hence the amount of current required to be carried on the primary power and ground distributions increases beyond the capabilities of the distribution lines. One solution to this problem involves making the primary power and ground distributions wider. However, certain minimum design distances such as D2 and D3 must be maintained so as to comply with the minimum feature requirements of the fabrication tools, for example. If the power and ground distributions are made wider, the device regions themselves must likewise be made wider, thus defeating higher cell integration. Moreover, an imbalance problem can arise even if the minimum feature requirements are maintained by increasing the size of a N device region, but without increasing the size of a P device region by a corresponding amount. This is because P devices are typically much weaker than N devices.
A second solution to the above-described current handling problem involves adding supplemental lines in metals 2 or 3.
FIG. 4 illustrates the technique of laying out supplemental line 110 in an east-west direction in metal 3 in parallel with primary power distribution 60 in metal 1. The primary and supplemental lines are connected through second insulator 100 and third insulator layer 105 by periodically provided stacked via and contacts 120. This solution effectively increases the width of the primary power distribution line. However, this effective increase in width may not be sufficient in extreme circumstances where many cells in the same row require current at the same time. Moreover, cells may have different dimensions, causing the primary distribution line to snake north and south and making it difficult to align the primary and supplemental lines.
FIG. 5 illustrates the technique of providing supplemental lines in metal 2. In this technique, supplemental power lines 115 are laid out in metal 2 in a north-south direction forming a matrix with the underlying primary power distributions. Inter-layer contacts are periodically provided to connect the supplemental power lines 115 and primary power distribution lines 60. This technique permits the current in each of the primary power distributions 60 to be shared in parallel so that a "hot" row of devices can draw current from other primary power distributions 60 associated with other rows. It should be apparent from the foregoing that the same technique could be applied for ground as well as power.
Although providing supplemental lines in metal 2 improves the ability of the primary power and ground distributions to provide desired amounts of current, other problems are created. For example, the supplemental line 115 in metal 2 can interfere with metal 1 pin locations and thus can prevent picking up device input and output pins. This further problem is illustrated in FIG. 6. As can be seen, when supplemental line 115 is laid out as shown in dashed lines, pin 85 is blocked, preventing any connection thereto unless a metal 1 interconnection can be made, which is unlikely. Accordingly, either the cell must be made wider or gaps must be provided between cells over which to lay out the supplemental line 115, as shown in FIG. 6. FIG. 7 is a side view of the cell in FIG. 6 taken along sectional line 7--7. As should be clear, either widening the cell or providing larger gaps between cells defeats higher cell integration.
Accordingly, there remains a need in the art for effective primary power and ground distributions in a basic cell that provides sufficient current handling ability while not impeding metal 1 routability or increased integration. The present invention fulfills this need.